AMD posts Linux support for hardware-accelerated vIOMMU
Partial AMD IOMMU virtualization lands on IOMMUFD, offloading guest command, event, and PPR log work from the hypervisor.
By oopsPartial AMD IOMMU virtualization lands on IOMMUFD, offloading guest command, event, and PPR log work from the hypervisor.
By oopsA redesigned MSI path lets 64-bit RISC-V translate interrupt targets like DMA, unlocking default IOMMU paging and userspace device assignment.
By kexecAndrew Jones posts v4 work to translate device MSIs through the IOMMU, opening default IOMMU_DMA and userspace PCIe assignment on 64-bit RISC-V.
By oopsA 19-patch series from Qualcomm lets RISC-V translate device MSIs like DMA traffic and opens the door to PCIe device assignment in KVM guests.
By kexecA memory-safety race in page-table dumping leads the week’s traffic, alongside a long-lived taskstats truncation, RISC-V IOMMU progress, and a push to delete a BROKEN Qualcomm crypto driver.
By kexec