RISC-V IOMMU gains MSI remapping, default DMA-IOMMU, and VFIO

A patch series from Andrew Jones adds MSI remapping to the RISC-V IOMMU, removing the main obstacle to turning on the kernel's standard DMA-IOMMU path by default and to VFIO device assignment on the architecture.

RISC-V could already translate device DMA, but Message Signaled Interrupts were different. The IMSIC MSI target address moves with interrupt affinity, one supervisor page per CPU, so earlier attempts either identity-mapped those pages as a workaround or built a heavyweight architecture-specific IRQ domain and mapping table. Feedback from Jason Gunthorpe pointed at a simpler model: extend the existing MSI prepare path so an ordered list of physical MSI targets becomes one contiguous IOVA range.

In the new design the IMSIC driver builds that full per-CPU address list and hands it to the IOMMU layer when an IRQ is allocated. DMA-IOMMU and iommufd map, install, roll back, and replay the range as a unit, caching the base IOVA on the MSI descriptor. Composition then picks the current CPU's target with ordinary arithmetic, including on affinity changes, without allocating memory or touching IOMMU state in atomic context. Devices that do not need IOMMU MSI translation still use physical addresses on the same path.

With remapping in place, work from Tomasz Jeznach enables IOMMU_DMA for 64-bit RISC-V, advertises cache-coherency capability only for DMA-coherent devices (required by VFIO and iommufd), turns on VFIO Type1 and KVM VFIO notification, and adds the options to the default RISC-V config. The practical result is that RISC-V can use paging domains by default and assign devices to userspace and VMs the way other major architectures already do.