RISC-V gains IOMMU MSI remapping, unlocking DMA and VFIO by default

RISC-V systems can finally use the kernel's standard IOMMU DMA path and VFIO device assignment after a redesign that remaps Message Signaled Interrupts the same way it remaps DMA.

Until now, the RISC-V IOMMU translated device DMA but left MSI targets as physical addresses. That gap blocked IOMMU_DMA and paging domains on the architecture and kept VFIO (and thus assigning devices into VMs) off the table. Andrew Jones's sixth revision of the series closes it by teaching the stack to treat every possible host IMSIC MSI page as one ordered physical list, then map that list into a single contiguous IOVA range.

The IMSIC driver builds the per-CPU target array once. On IRQ allocation it hands the full list to a new prepare helper used by both DMA-IOMMU and iommufd. Those backends install or reuse the whole range as a unit, cache the base IOVA on the MSI descriptor, and let message composition pick the current CPU's target with simple arithmetic, even across affinity changes, without IOMMU lookups in atomic context. iommufd's software-MSI bitmap grows on demand (capped at 16K entries) so it can cover one mapping per possible CPU, and range install/rollback keeps partially mapped windows from leaking across domain replacement.

A reserved software-MSI window is advertised for IMSIC devices: one page per possible CPU, based at 16 MiB so it stays below 4 GiB for 32-bit MSI registers and avoids the 128 MiB guest IMSIC placement used by common RISC-V VMMs. Jones notes that any fixed host window can still collide if a VMM puts a guest IMSIC on top of it; the choice only sidesteps known layouts.

With MSI remapping in place, Tomasz Jeznach's follow-ons turn on IOMMU_DMA for 64-bit RISC-V, VFIO_TYPE1, and KVM VFIO notification. The RISC-V defconfig now builds iommufd and VFIO PCI as modules, and the generic VFIO selftests gain riscv/riscv64 in their architecture filter. Devices that do not need IOMMU MSI translation continue to use physical addresses unchanged.