VFIO patches add CXL Type-2 accelerator passthrough for guests

NVIDIA engineer Manish Honap has posted a fourth revision of Linux kernel patches that add VFIO passthrough for CXL Type-2 accelerators, so a guest can drive its own virtual Host-managed Device Memory (HDM) decoder and reset the device without touching the host's physical decode path.

Type-2 devices pair an accelerator with coherent device memory. Until now, VFIO had no clean way to hand that memory window and the related control registers to a VM. The series targets a single, non-interleaved endpoint decoder: the host owns the physical decoder and the host physical address where device memory lands; the guest only chooses a guest physical address and sees virtualized register state.

Register emulation now lives in a separate vfio-cxl module that vfio-pci loads on demand, rather than behind an opaque handle in the CXL core. That redesign, which grew the series from 11 patches to 27, answers feedback from Dan Williams and pulls in the reset handling left out of the previous round. Guest writes to the HDM control block and CXL DVSEC stay in per-open shadows with CXL r4.0 field semantics, so a tenant cannot reprogram host decode, lock bits, or capability and range fields. The HDM window is exposed as a dedicated mmap-able VFIO region, with optional memory-failure containment so a poison event becomes a SIGBUS to the holder instead of a host failure.

Resets (ioctl, FLR, bus hot reset, and guest-initiated CXL reset through the DVSEC) resample decoder state after the hardware settles, and mappings are revoked across power and Memory Space transitions so a guest cannot keep live PTEs into a quiesced device. A module parameter and per-device flag let operators or variant drivers opt out and fall back to plain vfio-pci. Documentation records the address model, region layout, and kernel/VMM split for the supported topology.