QEMU RFC brings named Arm64 CPU models to KVM for live migration

QEMU today can only boot Arm64 guests under KVM with the catch-all host or max CPU types. That makes live migration between machines with different feature sets unreliable, because the guest sees whatever the source host happens to expose.

Khushit Shah of Nutanix has posted a fourth RFC on the QEMU development list that would fix that gap. It introduces hierarchical named CPU models for Arm64 under KVM. Each name is a fixed contract: the same model is meant to present the same guest-visible ID registers on any host that can run it. Operators can still tweak individual register fields on the command line when they need a narrower feature set.

The series seeds the hierarchy with an Armv9.0-A baseline, then Neoverse V2 revisions, plus cloud-oriented leaves for AWS Graviton4 and NVIDIA Grace derived from real silicon dumps. Performance monitoring is deliberately left out of named models because the host PMU is not portable across heterogeneous machines.

On the management side, the RFC adds the QMP introspection Arm has lacked relative to x86: listing which models a host can run and what blocks the others, expanding a model to its full property set, and a new query that reports the values the host actually supports for each property. The goal is feature parity so existing orchestration tooling can consume Arm named models with little change.

The work also hardens the boundary against leaking host features QEMU does not yet know about, rejecting unknown non-zero ID registers in the architecture’s reserved space. The series remains an RFC; it has not been merged.