Linux netdev adds fwnode PCS provider API for external serdes

Linux networking is getting a firmware-node producer-consumer API for Physical Coding Sublayer (PCS) devices, the blocks between a MAC and the rest of the physical layer that handle framing, scrambling, and encoding. Christian Marangi has posted the work for net-next, with the aim of registering PCS the way clocks and PHYs already work: providers expose devices, consumers look them up, and probe deferral plus driver removal are handled cleanly.

The change addresses a design debt. Early phylink allowed MAC drivers wide latitude in how they picked a PCS, which was fine when the coding layer lived in the same driver as the MAC. With 10G spreading into consumer and edge SoCs, PCS blocks increasingly sit outside the MAC, and ad-hoc selection has become hard to maintain. Marangi’s approach returns control to phylink. A MAC either keeps the older select callback or declares how many PCS instances it can use and which interface modes need a dedicated PCS; offering both is rejected at create time. Phylink keeps its own copy of supported interfaces so that list can change when a PCS is added or removed after the link exists.

A notifier path covers the lifetime races that made external PCS awkward: when a provider appears or disappears after phylink is running, matching PCS entries are attached or dropped, supported interfaces are refreshed, and a reconfiguration is forced when the active PCS is gone or restored. Device-tree and ACPI consumers parse a pcs-handle property; simple single-PCS providers get a stock translator, and more complex layouts supply their own. New subsystem documentation and an updated SFP migration guide ship with the work, and Marangi is listed as maintainer of the Ethernet PCS subsystem. Daniel Golle co-developed the fwnode provider core.

The first in-tree user is Airoha’s AN7581, which exposes multiple serdes PCS blocks for Ethernet, PON, PCIe, and USB with modes including USXGMII, 10GBASE-R, 2500BASE-X, 1000BASE-X, and SGMII. Bindings, a PCS provider driver, and phylink wiring for the SoC’s GDM ports (including external PHY or SFP cages via pcs-handle) land alongside the core API. Maxime Chevallier tested and reviewed portions of the series. According to Marangi, a parallel implementation from another developer was set aside once the late attach and remove races were covered.