Intel proposes upstreaming PISA GPU backend to LLVM

Intel has proposed upstreaming a new LLVM backend for PISA, a portable virtual instruction set architecture for Intel GPUs. The backend would give the open-source compiler a stable target that sits between high-level languages such as C++, OpenCL, and SYCL and the final hardware-specific ISA produced by a separate finalizer.

PISA is designed so one compiled module can run across multiple Intel GPU generations without source recompilation, while still supporting inline assembly for fine-grained control. Unlike vendor-neutral SPIR-V, it is Intel-specific. It uses named virtual registers with explicit sizes but a largely untyped model: the meaning of a register depends on the instruction that uses it. The memory model follows OpenCL-style address spaces and a C++-based consistency model with scopes. The backend is built exclusively on GlobalISel and until now has lived in an internal Intel repository.

Michal Paszkowski of Intel posted the RFC and began landing an initial stack of patches covering target registration, intrinsics, the machine-code layer, and GlobalISel lowering and selection. He argued that an in-tree PISA backend would complete LLVM’s picture of GPU code generation across the major vendors and remove the need for private forks when targeting Intel hardware.

Community members quickly compared the work to the existing NVPTX backend. Artem Belevich noted that unlimited virtual registers remain a recurring source of launch failures or forced spilling once a later tool maps them onto limited physical register files, and that external finalizers make reliable testing harder. Joseph Huber asked whether PISA would appear as a first-class Clang target triple or remain an intermediate step in a longer pipeline. Others suggested the deeper question of whether Machine IR is the right representation for virtual ISAs at all, and whether LLVM should eventually offer a lighter lowering path for such targets.

Paszkowski replied that an in-tree PISA verifier and textual assembler will let ordinary LIT tests catch many problems without hardware, and that integration with Intel’s public Compute Runtime will later supply an end-to-end executable path. Register-pressure hints and other cross-target improvements, he said, can be tackled separately. The backend is expected to land as experimental and stabilize in-tree before any promotion to official status.