DRM series adds HDMI 2.0 scrambling for Rockchip DW HDMI QP

A large patch series from Collabora's Cristian Ciocaltea brings HDMI 2.0 display modes, including 4K at 60 Hz, to the Synopsys DesignWare HDMI QP transmitter used in Rockchip RK3576 and RK3588 SoCs.

Rates above the classic 340 MHz TMDS ceiling need the source to program the sink over SCDC for high TMDS clock ratio and scrambling. The work adds that lifecycle to the DRM core and the DW HDMI QP bridge: decide when a mode needs scrambling, enable and monitor it, and restore SCDC after a disconnect. Because SCDC state is lost when a sink unplugs, connector detection must trigger a CRTC reset so the link is reprogrammed on reconnect rather than left half-configured.

Supporting that cleanly meant reshaping HDMI connector setup in DRM. An HDMI version enum lands first. Vendor and product strings, supported formats, max bits per component, and new limits for HDMI version and TMDS character rate move into an HDMI callbacks structure instead of lengthening the init helper's argument list. Callers convert through a temporary dual signature so the final API can take the original name without a noisy mass rename, then the transitional path and duplicated connector fields go away. KUnit tests cover scrambler callback pairing rules, TMDS limits inferred from version or set explicitly, and whether scrambler_needed tracks the 340 MHz threshold for HDMI 2.0 connectors.

Rockchip platform wiring, PHY hotplug helpers, and SCDC source-version advertisement round out the stack. Diederik de Haas reported successful runs on a NanoPC-T6 LTS and a Radxa Rock 5B.

Automated review flagged that the new version enum lists HDMI 2.2, a specification that does not exist; the latest major HDMI Forum family is 2.1.